Job Description ID- JDAS015
Overview:
Responsible for designing, implementing, and verifying high-performance, safety-compliant IPs in accordance with industry standards such as ISO 26262.
Key Responsibilities:
RTL Design Implementation & FuSa Compliance:
- Develop high-quality RTL designs for safety-critical semiconductor IPs using Verilog/SystemVerilog/VHDL.
- Ensure IP design meets FuSa requirements per ISO 26262/IEC 61508 and industry best practices.
Safety Mechanisms Diagnostics & Verification:
- Implement and validate safety mechanisms such as ECC, CRC, watchdog timers, and redundancy techniques.
- Work closely with the verification team to define and execute safety verification plans using UVM methodologies.
Safety Analysis & Tool Chain & Methodologies :
- Collaborate with safety architects to perform FMEDA (Failure Modes, Effects, and Diagnostic Analysis) and other safety assessments.
- Utilize industry-standard tools (e.g., Synopsys, Cadence, Mentor) for RTL synthesis, static timing analysis (STA), and linting.
Collaboration & Documentation :
- Work cross-functionally with system architects, verification engineers, and functional safety teams to ensure compliance with safety and performance requirements.
- Generate technical documentation, safety work products, and support safety certification processes.